`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:11:24 10/04/2011
// Design Name:   RAM
// Module Name:   C:/Users/david/16bitcpu/RAM_test.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RAM
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module RAM_test;

	// Inputs
	reg CLK;
	reg reset;
	reg w_en;
	reg clk_en;
	reg [15:0] data_in;
	reg [9:0] addr;

	// Outputs
	wire [15:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	RAM uut (
		.CLK(CLK), 
		.reset(reset), 
		.w_en(w_en), 
		.clk_en(clk_en), 
		.addr(addr),
		.data_in(data_in), 
		.data_out(data_out)
	);

	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;
		w_en = 0;
		clk_en = 0;
		data_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		w_en=1;
		clk_en=1;
		addr=10'h000;
		data_in=42;

		#30
		w_en=0;
		clk_en=0;
		addr=10'h000;


		#30
		
		w_en=1;
		clk_en=1;
		
	end
      
	always begin
	
	#5 CLK=~CLK;
	end
		
endmodule

